Architectural-level instructions for microprocessors may be translated between an instruction set architecture (ISA) and a native architecture. In some microprocessors, software optimizations of the ISA instructions may execute comparatively more efficiently than the ISA instructions upon which those software optimizations were based. Some past approaches chained software optimizations to pass control from one software optimization to another. However, such approaches may be challenged by indirectly-branched processes because it may be difficult to determine the target of an indirect branch.